Atrenta Introduces Industry's First Predictive IC Verification Solution, Enabling Early Detection and Prevention of Critical Chip Bugs

1Team:Verify is a major advance in chip verification, the first solution to bring the benefits of best-of-breed assertion-based verification (ABV) to logic designers. With 1Team:Verify, designers can apply sophisticated ABV at the initial, RTL (register transfer level) stages of development, automatically and without any verification expertise.

"1Team:Verify takes a pre-emptive approach to verification," said Atrenta's Product Marketing Director, Mani Narayan. "IC designers can intercept bugs during RTL creation, when the time and cost of making corrections is negligible. This is a big improvement over the conventional scenario, where bugs can complicate downstream development and lead to costly redesigns, respins and even field failures. In many cases, 1Team:Verify can save months and millions of dollars."

Catches Elusive Functional Bugs

1Team:Verify not only catches bugs earlier, it detects many critical "corner-case" bugs that traditional simulation-based verification methods miss. Examples include errors involving clock domain crossings (CDCs), finite state machines (FSMs), handshake mechanisms and bus structures. 1Team:Verify can perform many of these checks automatically, without user intervention. In addition to its fully automatic checking, 1Team:Verify allows more experienced users to write their own assertions using the assertion language of their choice.

ABV Made Accessible

ABV is an important complement to traditional simulation-based verification. While simulation is inherently incomplete and explores only a few paths through the state space of a design, ABV can exhaustively verify design structures. Whereas cycle-based simulators are not intrinsically capable of detecting timing-dependent effects that underlie CDC errors and many other bugs, ABV can. And while simulation provides no means of tracing many problems to their source in the RTL, ABV provides feedback on exactly how and where the bugs occurred.

Until now ABV has demanded significant expertise, requiring hand-off of RTL designs to verification specialists, who then applied ABV. If bugs were found, the design was handed back to the RTL team for corrections, then back to the verification team for re-checking, and so on. 1Team:Verify minimizes these time-consuming iterations by allowing RTL designers to carry out many ABV checks themselves, automatically. 1Team:Verify generates and validates a large number of assertions (over 10,000 assertions for a 500,000-gate design on average), providing a high degree of verification coverage without any user intervention.

1Team:Verify can pinpoint functional corner-case bugs and hard-to-target problems that sneak through simulation. These include CDC errors such as cross-domain fan-ins, reconvergence, handshake violations, gray code and data hold violations; as well as FSM problems such as deadlocks between communicating state machines, unreachable states, transitions that may not fire due to asynchronous signals and FSM registers stuck at constant values. In addition to catching problems that conventional tools miss, 1Team:Verifiy minimizes the many false CDC violations that traditional tools over-report.

Support for User-Specified Assertions

Beyond its automated assertion checking, 1Team:Verify also makes it easy for non-expert users to specify their own assertions. It supports the open verification library (OVL) -- an Accellera-standard library of 31 predefined assertions from which users can choose. Extensions to OVL are also supported for users who want to define new assertions using the OVL paradigm. OVL, in turn, provides an excellent stepping-stone to powerful assertion languages such as PSL (Property Description Language) and SVA (System Verilog Assertions), which are both available as 1Team:Verify options. 1Team:Verify also features an integrated debug environment that enables designers to quickly track down the source of the problems.

1Team:Verify is part of a growing family of Predictive Development solutions from Atrenta. Other members include 1Team:Analyze, also unveiled today, and the recently introduced 1Team:Implement suite. 1Team:Analyze enables IC logic designers to predict and prevent RTL structural, coding and consistency issues, manage constraints and optimize designs for testability and power. 1Team:Implement enables IC architects, logic designers and implementation teams to optimize physical aspects of their designs, including timing, area and congestion.

About Atrenta

Atrenta Inc. is the leading provider of Predictive Development solutions for companies creating complex chips, systems and embedded software. Predictive Development is a new class of design automation solution that turns the costly and error-prone activity of electronic development into a more predictable, manageable and reliable process. Atrenta's 1Team Family of Predictive Development solutions enhances the entire development cycle-from architectural planning to physical implementation, and from hardware to embedded software. Atrenta is headquartered in San Jose, Calif., with a research and development center in Noida, India. For further information, visit the Atrenta website at http://www.atrenta.com/, email moreinfo@atrenta.com or call 408-453-333

NOTE: Atrenta is registered trademark and ITeam is a trademark of Atrenta Inc. All other trademarks belong to their respective owner.

CONTACT: Jane Evans-Ryan of MCA, +1-650-968-8900, or jryan@mcapr.com,
for Atrenta; or Atrenta Headquarters, Mona Singh, Marketing Communications
Manager of Atrenta Inc., +1-408-467-4248, or mona@atrenta.com

Web site: http://www.atrenta.com/